Projeto de arquitetura de um filtro para processamento de imagens utilizando processador nios ii e field programmable gate array (FPGA)
The use of Field Programmable Gate Array (FPGA) in embedded systems allows to combine the software flexibility with the hardware speed, in what is called reconfigurable computing, being able to implement, from simple processing to circuits such as video controller, including RAM memory, or even inco...
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| Main Authors: | , , , , , , |
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| Format: | Online |
| Language: | Portuguese |
| Published: |
Universidade Estadual de Campinas (UNICAMP)
2016
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| Subjects: | |
| Online Access: | https://econtents.sbu.unicamp.br/eventos/index.php/simtec/article/view/9263 |
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| Summary: | The use of Field Programmable Gate Array (FPGA) in embedded systems allows to combine the software flexibility with the hardware speed, in what is called reconfigurable computing, being able to implement, from simple processing to circuits such as video controller, including RAM memory, or even incorporate computationally demanding and complex processing. The desired circuit development project in FPGA may be developed through Altera&";s Quartus II program, which enables the electronic circuit development. The projected logic circuit programming is transferred to FPGA, through USB cable; after received and loaded, the FPGA carries out the programmed functions, and this is a volatile programming, that is, the device must be reprogrammed every time it is turned on. The transference may be eliminated with the use of a programmable ROM memory or a solid-state disk, which enables the project to be directly loaded to the FPGA when turned on. This work presents an architecture for the digital signal processing through devices implemented in hardware through convolution networks (ConvNets), networks with multiple layers that implement convolution filters. On the image processing, the algorithms are, in general, implemented in software; therefore, the computational performance may not be adapted or meet real-time application requirements. In this case, the 2D convolution may be applied in a concurrent and/or parallel way, which may be obtained with exploitation of the FPGAs potential through ConvNets, therefore, obtaining potentially much higher performance. |
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| ISSN: | 2525-5398 |
